RISC vs CISC

Compare and contrast CISC architecture and RISC architecture. Make sure to include the strengths and weaknesses of each as well as applications to which they would be most suited. You may also compare/contrast them with any architecture that may be considered as future replacements for either or both of these two.

The aim of CISC architecture is to do more with fewer instructions, and so the instructions passed to a CPU within CISC are much more complicated. Because of this CPU - oriented approach, the software compiler that essentially feeds the instructions has to do less work. Fewer, more complicated instructions need a smaller amount of storage space and therefore the computer needs less RAM. CISC architecture was therefore ideal in a time when the price of RAM was much more expensive when compared to today's prices, and when the software working with the architecture was inferior.

RISC architecture takes the opposite approach to CISC; it is designed to receive many more simple instructions. RISC allows a number of performance - enhancing techniques to be applied. One such is pipelining - "the technique of allowing the steps in the machine cycle to overlap" (Brookshear, 2007: 124). Another is caching, where because less CPU 'real estate' is required to process the much simpler instruction set, more general purpose registers can be made available which the CPU can use to store a copy of the main memory at any given time and save the time normally taken to communicate with main memory.

Both architectures have drawbacks. CISC allows for much less flexibility in software because the more complicated instruction set that it processes are more rigid in terms of allocating memory and processing programs. Also, CISC cannot implement pipelining because the instructions are always different lengths. While RISC is now more dominant in the processor market (and is the basis behind future processor technology as I will explain below) it is only as good as the software that supports it. Compilers must do much more to simplify the instructions to a level that RISC can process, and for this reason RISC struggled to gain a foothold in the 1980s and 1990s. Software companies such as Microsoft didn't back it - "Windows 3.1 and Windows 95 were designed with CISC processors in mind" (Chen, Novick & Shimano, 2000).

In the last five years the regular increase in performance brought about by each new release of a CPU has slowed, and manufacturers such as Intel and AMD are designing future processors to take advantage of multithreading rather than trying to squeeze in more instructions per clock cycle. Probably the best known of these next generation CPU's is Intel's Itanium which is built on Explicitly Parallel Instruction Computing (EPIC) architecture. This improves in RISC by making the compiler and processor work together to measure how many of the operations in a program can be performed simultaneously, and again much more responsibility for this is passed to the compiler. More space is again allocated to cache memory and also to adding extra cores to the processor. These extra cores allow multiple threads to be executed simultanteously - a huge advantage in the field of virtualisation, for example, because one operating system can be run from each core and the physical size of server farms can be greatly reduced. "Itanium's advantages in instruction level parallelism (ILP) and relatively small cores will give it a clear performance lead over its RISC and CISC rivals as semiconductor technology advances" (Feldman, 2006).

It is clear, however, that today's design techniques are limited; "developers of artificial neural networks argue that the basic CPU - main memory design model is inefficient when compared to the human brain because most of the connectivity is destined to be idle most of the time" (Brookshear, 2007: 125).

References:

Brookshear, G, J. (2007) Computer Science: An Overview 9th ed. Boston: Pearson Education Inc.

Chen, C., Novick, G. & Shimano, K (2000) "risc vs cisc" [Online]
Available from http://cse.stanford.edu/class/sophomore-college/projects-00/risc/about/index.html (Accessed 22nd November 2007)

Feldman, M. (2006) "Itanium's Growing Pains" [Online] Santa Fe, USA: Tabor Publications and Events
Available from http://www.hpcwire.com/hpc/640152.html (Accessed: 22nd November 2007).